A cyclic redundancy check (CRC) is used to detect errors in stored or transmitted data. A CRC is calculated using an algorithm which divides the data block by a generator polynomial to produce a remainder. This remainder is the CRC and it is usually appended to the data block before it is transmitted or stored. When the block of data with the appended CRC is received or retrieved from storage, the CRC algorithm is applied to the data block for a second time and may be compared with the originally calculated CRC. If they are identical, the data block is said to contain no errors with a known confidence interval. If the two CRCs do not match, then the data contains an error.
CRC algorithms and their methods of application are known. In one method, known as the feedback method, the message or block of data for which the CRC is calculated must be augmented by appending n zero's to the message, where n is the number of bits in the CRC (i.e. the order of the generator polynomial). An alternative for implementing a CRC algorithm known as the feed forward method does not require augmentation of the message.
A CRC calculation can be implemented in hardware using shift register arrangements which are known. In the feedback method, n zeros are pushed through the register after the original message. Using the feed forward method, the CRC registers contain the CRC value for the message as soon as the last bit of the message arrives. This is particularly useful in transmission systems where the CRC must be appended immediately after the message or data block. In contrast, using the feedback method, the system would need to wait an additional n clock cycles until the CRC calculation is complete.
CRC circuits can be built using digital logic and may be implemented in programmable logic devices such as Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). This hardware can be designed either with schematics or using a language which describes digital electronic systems such as VHDL (VHSIC Hardware Description Language) and Verilog®. Once the VHDL or Verilog® code is written to describe the desired behavior of the digital logic circuit, it can be synthesized by using a development tool suitable for the target device to create the final hardware with the desired function or behavior. Digital logic CRC calculators can also be designed to work on a word or an m-bit bus instead of a single bit serial stream. Such CRC calculators are often created using tools such as code generators. For example, to design a CRC calculator capable of working on an m-bit bus, a code generator, for example written in ‘C’, Perl or other programming language is used. Code generators generate synthesizable High Level Description language (HDL) code such as VHDL or Verilog® based on specific input parameters which are accepted by the code generator. In the case of a CRC calculator for an m-bit bus, these parameters are (i) the CRC generator polynomial and (ii) data bus width. Therefore, the code generator generates HDL code for a logic circuit specific to the CRC generator polynomial and word or data bus width that are passed as inputs to the code generator program.
A limitation of this method of creating CRC calculators is each time a new CRC generator polynomial (i.e. a polynomial with more or less terms) is to be used in the CRC calculator, a designer must use the code generator to produce new HDL code suitable for that polynomial and data word width combination. That is, the HDL code created by the code generator is specific to each CRC polynomial and data word width combination. Therefore the HDL code is not transportable across a range of combinations and unique HDL code is required for every polynomial and data word width combination. This consumes valuable programming resources and ultimately results in an undesirable delay between identifying a new generator polynomial and word/bus width combination and providing a suitable CRC calculator circuit.
In addition to these limitations, the code produced using existing methods for creating a CRC calculator results in logic with maximum operating frequencies which are less than desirable for real time calculation of CRCs in certain applications. Further, they do not allow the designer to make a trade off between the maximum frequency of operation and silicon area, using a single value setting that is specified as a parameter that is passed to the HDL code module.